# Project Proposal: SRAM-backed LSTM Accelerator for ECG Classification

## Track: A (Digital / Mixed-Signal)

## Team: Waibibabu

### Team Members

| Name | Role |
|------|------|
| Xuhe | Architecture & RTL Design |
| Hank | Model, Quantization & Verification |
| CC | Layout, DRC/LVS & Signoff |
| Sam | Integration, Testbench & Documentation |

---

## Decision Update

**Final direction:** LSTM + SRAM time-series inference accelerator.

**Validation task:** ECG waveform normal / abnormal classification.

The earlier Transformer direction is no longer part of the current project delivery scope. It remains only as archived reference material.

---

## Overview

This project implements a compact quantized LSTM accelerator on the GF180 MCU process. The accelerator receives ECG sequence data through an SPI-driven test interface, reads quantized LSTM weights from on-chip SRAM, performs inference, and returns a Normal / Abnormal classification result.

The goal is not to build a large general-purpose neural accelerator. The goal is to complete a focused, verifiable, and layout-friendly LSTM datapath that can be taken through RTL, simulation, synthesis, layout, STA, and signoff within the Chipathon schedule.

---

## Application: ECG Validation

ECG is a good validation target because it is a real time-series biomedical signal with interpretable temporal structure:

- P wave, QRS complex, and T wave morphology
- R-R interval timing
- rhythm regularity / irregularity
- abnormal patterns such as atrial fibrillation, premature beats, and ventricular tachycardia

The first hardware validation target is a two-class task:

| Class | Meaning | Expected output |
|-------|---------|-----------------|
| Normal | ECG segment follows normal rhythm and morphology | `0` or Normal probability |
| Abnormal | ECG segment shows rhythm or morphology anomaly | `1` or Abnormal probability |

The Python model, quantized model, and RTL implementation must be compared against the same ECG test vectors.

---

## Architecture

```text
ECG segment
  -> preprocessing / feature packing
  -> SPI input buffer
  -> SRAM-backed quantized LSTM datapath
  -> classifier head
  -> SPI result + done interrupt
```

### Main Blocks

| Block | Function |
|-------|----------|
| SPI Control | Loads weights, loads ECG input vectors, starts inference, reads result/status |
| Input Buffer | Stores the active ECG sequence window or feature sequence |
| Weight SRAM | Stores quantized LSTM weights and biases |
| LSTM Datapath | Computes recurrent hidden state using fixed-point MAC operations |
| Classifier Head | Converts final hidden state into Normal / Abnormal output |
| Status / IRQ | Indicates inference completion and exposes simple error/status flags |

---

## Quantization Contract

| Parameter | Initial target |
|-----------|----------------|
| Weights | 4-bit signed |
| Activations | 8-bit signed |
| Bias | 8-bit signed |
| Accumulator | Fixed-point width selected after Python range analysis |
| Hidden dimension | 8-32, depending on area and accuracy tradeoff |
| Weight storage | Around 4KB SRAM target |

The exact hidden dimension and accumulator width should be finalized after the ECG baseline model and quantization sweep.

---

## I/O Specification

| Signal | Direction | Description |
|--------|-----------|-------------|
| `clk` | Input | System clock |
| `rst_n` | Input | Active-low reset |
| `spi_sclk` | Input | SPI clock |
| `spi_cs_n` | Input | SPI chip select |
| `spi_mosi` | Input | Weight / ECG input stream |
| `spi_miso` | Output | Classification result / status readback |
| `irq_done` | Output | Inference complete interrupt |
| `vdd` | Power | Core supply |
| `vss` | Ground | Core ground |
| `io_vdd` | Power | I/O supply |
| `io_vss` | Ground | I/O ground |

---

## Verification Plan

### Model-Level Verification

1. Prepare ECG segments and labels.
2. Train a small LSTM baseline in Python.
3. Quantize weights and activations.
4. Export fixed-point test vectors for RTL simulation.

### RTL Verification

1. Load weights through SPI.
2. Load ECG sample sequence through SPI.
3. Run inference.
4. Read output classification and status.
5. Compare RTL output against the quantized Python golden model.

### Hardware Flow Verification

1. Synthesize with Yosys / LibreLane.
2. Run gate-level simulation where practical.
3. Check timing with OpenSTA.
4. Complete place and route.
5. Run DRC/LVS signoff checks.

---

## Performance Targets

| Metric | Target |
|--------|--------|
| Area | Below 500um x 500um target envelope |
| Clock frequency | Around 50MHz initial target |
| Weight capacity | Around 4KB |
| Task | ECG Normal / Abnormal classification |
| Main evidence | Python model, quantized model, RTL simulation, and layout reports |

---

## Implementation Plan

### Phase 1: ECG Baseline and Interface Contract

- Select ECG segment length and feature representation.
- Train a small LSTM model.
- Define fixed-point scaling and quantization.
- Freeze SPI command format and register map.

### Phase 2: RTL Implementation

- Implement SPI loader and control FSM.
- Implement input buffer and weight SRAM access path.
- Implement quantized LSTM MAC datapath.
- Implement classifier output and status registers.

### Phase 3: Simulation and Cross-Checking

- Build Python golden vector export.
- Run RTL simulation with ECG vectors.
- Compare class result and intermediate fixed-point values.
- Debug overflow, saturation, and scaling issues.

### Phase 4: RTL2GDS

- Synthesize with GF180 libraries.
- Floorplan, place, route, and close timing.
- Generate area, timing, power, and signoff reports.
- Package final GDS and project documentation.

---

## Scope Boundaries

### In Scope

- LSTM + SRAM inference datapath.
- SPI-based weight and ECG data loading.
- ECG Normal / Abnormal classification validation.
- RTL-to-GDS implementation on GF180.

### Out of Scope for Current Delivery

- SD card Transformer accelerator.
- EMG, EEG, or industrial vibration as primary demos.
- Online learning as a required feature.
- Large multi-class biomedical diagnosis.

---

## Differentiation

| Feature | This proposal |
|---------|---------------|
| Application | ECG time-series classification |
| Model | Small quantized LSTM |
| Hardware focus | SRAM-backed recurrent inference |
| Verification focus | ECG golden vectors from Python to RTL |
| Schedule fit | Focused scope suitable for Chipathon delivery |

---

## References

- Hochreiter, S., & Schmidhuber, J. (1997). Long Short-Term Memory.
- GF180 MCU PDK documentation.
- LibreLane RTL-to-GDS flow documentation.
- Public ECG datasets such as MIT-BIH style arrhythmia records may be used for model development, subject to preprocessing and licensing checks.

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*Last updated: 2026-06-10*